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| SL74HC251 8-Input Data Selector/Multiplexer with 3-State Outputs High-Performance Silicon-Gate CMOS The SL74HC251 is identical in pinout to the LS/ALS251. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The device selects one of the eight binary Data Inputs, as determined by the Address Inputs. The Output Enable pin must be at a low level for the selected data to appear at the outputs. If Output Enable is high, the Y and the Y outputs are in the high-impedance state. This 3-State feature allows the IN74HC251 to be used in bus-oriented systems. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC251N Plastic SL74HC251D SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs A2 X L L L L PIN 16 =VCC PIN 8 = GND H H H H A1 X L L H H L L H H A0 X L H L H L H L H OE H L L L L L L L L Outputs Y Z D0 D1 D2 D3 D4 D5 D6 D7 Y Z D0 D1 D2 D3 D4 D5 D6 D7 D0,D1...D7=the level of the respective D input Z = high-impedance state X = don't care SLS System Logic Semiconductor SL74HC251 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 25 50 75 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HC251 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 0.5 85 C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 5.0 125 C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 10 A A V Unit VIH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA IOUT 5.2 mA 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOH V VOL Maximum Low-Level Output Voltage VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA IOUT 5.2 mA IIN IOZ Maximum Input Leakage Current Maximum Three-State Leakage Current VIN=VCC or GND Output in High-Impedance State VIN= VIL or VIH VOUT=VCC or GND VIN=VCC or GND IOUT=0A ICC Maximum Quiescent Supply Current (per Package) 6.0 8.0 80 160 A SLS System Logic Semiconductor SL74HC251 AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input t r=t f=6.0 ns) VCC Symbol tPLH, t PHL Parameter Maximum Propagation Delay, Input D to Output Y or Y (Figures 1,2 and 5) Maximum Propagation Delay , Input A to Output Y or Y (Figures 3 and 5) Maximum Propagation Delay , Output Enable to Output Y (Figures 4 and 6) Maximum Propagation Delay , Output Enable to Output Y (Figures 4 and 6) Maximum Propagation Delay , Output Enable to Output Y (Figures 4 and 6) Maximum Propagation Delay , Output Enable to Output Y (Figures 4 and 6) Maximum Output Transition Time, Any Output (Figures 1 and 6) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State) Power Dissipation Capacitance (Per Package) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to -55C 185 37 31 205 41 35 195 39 33 145 29 25 220 44 37 150 30 26 75 15 13 10 15 85C 230 46 39 255 51 43 245 48 42 180 36 31 275 55 47 190 38 33 95 19 16 10 15 125C 280 56 48 310 62 53 295 59 50 220 44 38 330 66 56 225 45 38 110 22 19 10 15 Unit ns tPLH, t PHL ns tPLZ, t PHZ ns tPZL, t PZH ns tPLZ, t PHZ ns tPZL, t PZH ns tTLH, t THL ns CIN COUT pF pF Typical @25C,VCC=5.0 V 36 pF Figure 1. Switching Waveforms Figure 2. Switching Waveforms SLS System Logic Semiconductor SL74HC251 Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Test Circuit Figure 6.Test Circuit EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor |
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